RocketLogger 2.1.0
check_config.c
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1
32#include <stddef.h>
33#include <stdint.h>
34#include <stdio.h>
35#include <stdlib.h>
36
37#include <fcntl.h>
38#include <sys/mman.h>
39#include <sys/stat.h>
40#include <sys/types.h>
41#include <unistd.h>
42
43
44// Clock Management module register base addresses, offsets and sizes
46#define CM_PER_BASE 0x44E00000
47#define CM_PER_SIZE 0x0400
48
49#define L4LS_CLKSTCTRL_OFFSET 0x00
50#define L4LS_CLKCTRL_OFFSET 0x60
51#define EPWMSS1_CLKCTRL_OFFSET 0xCC
52#define EPWMSS0_CLKCTRL_OFFSET 0xD4
53#define EPWMSS2_CLKCTRL_OFFSET 0xD8
54#define PRU_ICSS_CLKCTRL_OFFSET 0xE8
55
56
57// CONTROL module register base addresses, offsets and sizes
59#define CONTROL_BASE 0x44E10000
60#define CONTROL_SIZE 0x20000
61
62#define PWMSS_CTRL_OFFSET 0x664
63#define CONF_GMPC_AD14_OFFSET 0x838 /* nDR1 pin, PRU0 controlled */
64#define CONF_GMPC_AD15_OFFSET 0x83C /* nDR0 pin, MUX_MODE6 for PRU0 controlled, MUX_MODE5 for pr1_ecap0_ecap_capin_apwm_o */
65#define CONF_GMPC_A2_OFFSET 0x848 /* Latch reset A pin, ehrpwm1A controlled */
66#define CONF_GMPC_A3_OFFSET 0x84C /* Latch reset B pin, ehrpwm1B controlled */
67#define CONF_SPI0_SCLK_OFFSET 0x950 /* ADC clock pin, ehrpwm0A controlled */
68
69// PWM module register base addresses, offsets and sizes
71#define PWM0_BASE 0x48300000
73#define PWM1_BASE 0x48302000
75#define PWM2_BASE 0x48304000
76
78#define PWMSS_OFFSET 0x0000
80#define ECAP_OFFSET 0x0100
82#define EQEP_OFFSET 0x0180
84#define EPWM_OFFSET 0x0200
85
87#define PWM_SIZE 0x0260
89#define PWMSS_SIZE 0x0100
91#define ECAP_SIZE 0x0080
93#define EQEP_SIZE 0x0080
95#define EPWM_SIZE 0x0060
96
97// PWMSS sub-module register base addresses, offsets and sizes
98
100#define PWMSS0_BASE (PWM0_BASE + PWMSS_OFFSET)
102#define PWMSS1_BASE (PWM1_BASE + PWMSS_OFFSET)
104#define PWMSS2_BASE (PWM2_BASE + PWMSS_OFFSET)
105
106// ePWM sub-module register base addresses, offsets and sizes
108#define EPWM0_BASE (PWM0_BASE + EPWM_OFFSET)
110#define EPWM1_BASE (PWM1_BASE + EPWM_OFFSET)
112#define EPWM2_BASE (PWM2_BASE + EPWM_OFFSET)
113
114// PWMSS configuration register offsets
116#define PWMSS_IDVER_OFFSET 0x00
118#define PWMSS_SYSCONFIG_OFFSET 0x04
120#define PWMSS_CLKCONFIG_OFFSET 0x08
122#define PWMSS_CLKSTATUS_OFFSET 0x0C
123
124// ePWM configuration register offsets
126#define EPWM_TBCTL_OFFSET 0x00
128#define EPWM_TBSTS_OFFSET 0x02
130#define EPWM_TBPHS_OFFSET 0x06
132#define EPWM_TBCNT_OFFSET 0x08
134#define EPWM_TBPRD_OFFSET 0x0A
136#define EPWM_CMPCTL_OFFSET 0x0E
138#define EPWM_CMPA_OFFSET 0x12
140#define EPWM_CMPB_OFFSET 0x14
142#define EPWM_AQCTLA_OFFSET 0x16
144#define EPWM_AQCTLB_OFFSET 0x18
145
147int main() {
149 int mem_fd = -1;
151 volatile uint8_t const *cm_per_mem = NULL;
153 volatile uint8_t const *control_mem = NULL;
155 volatile uint8_t const *pwm0_mem = NULL;
157 volatile uint8_t const *pwm1_mem = NULL;
158
159 // open /dev/mem for memory mapping
160 mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
161 if (mem_fd < 0) {
162 return EXIT_FAILURE;
163 }
164
165 // map CM_PER registers
166 cm_per_mem = (volatile uint8_t const *)mmap(0, CM_PER_SIZE, PROT_READ | PROT_WRITE,
167 MAP_SHARED, mem_fd, CM_PER_BASE);
168 if ((void *)cm_per_mem == MAP_FAILED) {
169 return EXIT_FAILURE;
170 }
171
172 // map CONTROL registers
173 control_mem = (volatile uint8_t const *)mmap(0, CONTROL_SIZE, PROT_READ | PROT_WRITE,
174 MAP_SHARED, mem_fd, CONTROL_BASE);
175 if ((void *)control_mem == MAP_FAILED) {
176 return EXIT_FAILURE;
177 }
178
179 // map PWM0 registers
180 pwm0_mem = (volatile uint8_t const *)mmap(0, PWM_SIZE, PROT_READ | PROT_WRITE,
181 MAP_SHARED, mem_fd, PWM0_BASE);
182 if ((void *)pwm0_mem == MAP_FAILED) {
183 return EXIT_FAILURE;
184 }
185
186 // map PWM1 registers
187 pwm1_mem = (volatile uint8_t const *)mmap(0, PWM_SIZE, PROT_READ | PROT_WRITE,
188 MAP_SHARED, mem_fd, PWM1_BASE);
189 if ((void *)pwm1_mem == MAP_FAILED) {
190 return EXIT_FAILURE;
191 }
192
193 // read memory mapped registers
194
195 // get pointers of CM_PER registers
196 volatile uint32_t const *cm_per_l4ls_clkstctrl =
197 (volatile uint32_t const *)(cm_per_mem + L4LS_CLKSTCTRL_OFFSET);
198 volatile uint32_t const *cm_per_l4ls_clkctrl =
199 (volatile uint32_t const *)(cm_per_mem + L4LS_CLKCTRL_OFFSET);
200 volatile uint32_t const *cm_per_epwmss0_clkctrl =
201 (volatile uint32_t const *)(cm_per_mem + EPWMSS0_CLKCTRL_OFFSET);
202 volatile uint32_t const *cm_per_epwmss1_clkctrl =
203 (volatile uint32_t const *)(cm_per_mem + EPWMSS1_CLKCTRL_OFFSET);
204 volatile uint32_t const *cm_per_epwmss2_clkctrl =
205 (volatile uint32_t const *)(cm_per_mem + EPWMSS2_CLKCTRL_OFFSET);
206 volatile uint32_t const *cm_per_pru_icss_clkctrl =
207 (volatile uint32_t const *)(cm_per_mem + PRU_ICSS_CLKCTRL_OFFSET);
208
209 printf("CM_PER registers:\n");
210 printf(" L4LS_CLKSTCTRL: \t0x%08x\n", *cm_per_l4ls_clkstctrl);
211 printf(" L4LS_CLKCTRL: \t0x%08x\n", *cm_per_l4ls_clkctrl);
212 printf(" EPWMSS0_CLKCTRL: \t0x%08x\n", *cm_per_epwmss0_clkctrl);
213 printf(" EPWMSS1_CLKCTRL: \t0x%08x\n", *cm_per_epwmss1_clkctrl);
214 printf(" EPWMSS2_CLKCTRL: \t0x%08x\n", *cm_per_epwmss2_clkctrl);
215 printf(" PRU_ICSS_CLKCTRL:\t0x%08x\n", *cm_per_pru_icss_clkctrl);
216
217 // get pointers of CONTROL registers
218 volatile uint32_t const *control_pwmss_ctrl =
219 (volatile uint32_t const *)(control_mem + PWMSS_CTRL_OFFSET);
220 volatile uint32_t const *control_conf_gpmc_ad14 =
221 (volatile uint32_t const *)(control_mem + CONF_GMPC_AD14_OFFSET);
222 volatile uint32_t const *control_conf_gpmc_ad15 =
223 (volatile uint32_t const *)(control_mem + CONF_GMPC_AD15_OFFSET);
224 volatile uint32_t const *control_conf_gpmc_a2 =
225 (volatile uint32_t const *)(control_mem + CONF_GMPC_A2_OFFSET);
226 volatile uint32_t const *control_conf_gpmc_a3 =
227 (volatile uint32_t const *)(control_mem + CONF_GMPC_A3_OFFSET);
228 volatile uint32_t const *control_conf_spi0_sclk =
229 (volatile uint32_t const *)(control_mem + CONF_SPI0_SCLK_OFFSET);
230
231 printf("CONTROL registers:\n");
232 printf(" PWMSS_CTRL: \t0x%08x\n", *control_pwmss_ctrl);
233 printf(" CONF_GMPC_AD14:\t0x%08x (ADC1 nDR)\n", *control_conf_gpmc_ad14);
234 printf(" CONF_GMPC_AD15:\t0x%08x (ADC0 nDR)\n", *control_conf_gpmc_ad15);
235 printf(" CONF_GMPC_A2: \t0x%08x (LATCH A reset)\n", *control_conf_gpmc_a2);
236 printf(" CONF_GMPC_A3: \t0x%08x (LATCH B reset)\n", *control_conf_gpmc_a3);
237 printf(" CONF_SPI0_SCLK:\t0x%08x (ADC clock)\n", *control_conf_spi0_sclk);
238
239 // get pointers of PWMSS0 registers
240 volatile uint32_t const *pwmss0_sysconfig =
241 (volatile uint32_t const *)(pwm0_mem + PWMSS_OFFSET + PWMSS_SYSCONFIG_OFFSET);
242 volatile uint32_t const *pwmss0_clkconfig =
243 (volatile uint32_t const *)(pwm0_mem + PWMSS_OFFSET + PWMSS_CLKCONFIG_OFFSET);
244 volatile uint32_t const *pwmss0_clkstatus =
245 (volatile uint32_t const *)(pwm0_mem + PWMSS_OFFSET + PWMSS_CLKSTATUS_OFFSET);
246
247 volatile uint16_t const *epwm0_tbctl =
248 (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_TBCTL_OFFSET);
249 volatile uint16_t const *epwm0_tbcnt =
250 (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_TBCNT_OFFSET);
251 volatile uint16_t const *epwm0_tbprd =
252 (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_TBPRD_OFFSET);
253 volatile uint16_t const *epwm0_cmpa =
254 (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_CMPA_OFFSET);
255 volatile uint16_t const *epwm0_cmpb =
256 (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_CMPB_OFFSET);
257 volatile uint16_t const *epwm0_aqctla =
258 (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_AQCTLA_OFFSET);
259 volatile uint16_t const *epwm0_aqctlb =
260 (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_AQCTLB_OFFSET);
261
262 printf("PWMSS0 registers:\n");
263 printf(" SYSCONFIG: \t0x%08x\n", *pwmss0_sysconfig);
264 printf(" CLKCONFIG: \t0x%08x\n", *pwmss0_clkconfig);
265 printf(" CLKSTATUS: \t0x%08x\n", *pwmss0_clkstatus);
266 printf(" ePWM0 registers:\n");
267 printf(" TBCTL: \t0x%04x\n", *epwm0_tbctl);
268 printf(" TBCNT: \t0x%04x\n", *epwm0_tbcnt);
269 printf(" TBPRD: \t0x%04x\n", *epwm0_tbprd);
270 printf(" CMPA: \t0x%04x\n", *epwm0_cmpa);
271 printf(" CMPB: \t0x%04x\n", *epwm0_cmpb);
272 printf(" AQCTLA:\t0x%04x\n", *epwm0_aqctla);
273 printf(" AQCTLB:\t0x%04x\n", *epwm0_aqctlb);
274
275 // get pointers of PWMSS1 registers
276 volatile uint32_t const *pwmss1_sysconfig =
277 (volatile uint32_t const *)(pwm1_mem + PWMSS_OFFSET + PWMSS_SYSCONFIG_OFFSET);
278 volatile uint32_t const *pwmss1_clkconfig =
279 (volatile uint32_t const *)(pwm1_mem + PWMSS_OFFSET + PWMSS_CLKCONFIG_OFFSET);
280 volatile uint32_t const *pwmss1_clkstatus =
281 (volatile uint32_t const *)(pwm1_mem + PWMSS_OFFSET + PWMSS_CLKSTATUS_OFFSET);
282
283 volatile uint16_t const *epwm1_tbctl =
284 (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_TBCTL_OFFSET);
285 volatile uint16_t const *epwm1_tbcnt =
286 (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_TBCNT_OFFSET);
287 volatile uint16_t const *epwm1_tbprd =
288 (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_TBPRD_OFFSET);
289 volatile uint16_t const *epwm1_cmpa =
290 (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_CMPA_OFFSET);
291 volatile uint16_t const *epwm1_cmpb =
292 (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_CMPB_OFFSET);
293 volatile uint16_t const *epwm1_aqctla =
294 (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_AQCTLA_OFFSET);
295 volatile uint16_t const *epwm1_aqctlb =
296 (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_AQCTLB_OFFSET);
297
298 printf("PWMSS1 registers:\n");
299 printf(" SYSCONFIG: \t0x%08x\n", *pwmss1_sysconfig);
300 printf(" CLKCONFIG: \t0x%08x\n", *pwmss1_clkconfig);
301 printf(" CLKSTATUS: \t0x%08x\n", *pwmss1_clkstatus);
302 printf(" ePWM1 registers:\n");
303 printf(" TBCTL: \t0x%04x\n", *epwm1_tbctl);
304 printf(" TBCNT: \t0x%04x\n", *epwm1_tbcnt);
305 printf(" TBPRD: \t0x%04x\n", *epwm1_tbprd);
306 printf(" CMPA: \t0x%04x\n", *epwm1_cmpa);
307 printf(" CMPB: \t0x%04x\n", *epwm1_cmpb);
308 printf(" AQCTLA:\t0x%04x\n", *epwm1_aqctla);
309 printf(" AQCTLB:\t0x%04x\n", *epwm1_aqctlb);
310
311 // unmap memory
312 if (cm_per_mem != NULL) {
313 munmap((void *)cm_per_mem, CM_PER_SIZE);
314 cm_per_mem = NULL;
315 }
316 if (control_mem != NULL) {
317 munmap((void *)control_mem, CONTROL_SIZE);
318 control_mem = NULL;
319 }
320 if (pwm0_mem != NULL) {
321 munmap((void *)pwm0_mem, PWM_SIZE);
322 pwm0_mem = NULL;
323 }
324 if (pwm1_mem != NULL) {
325 munmap((void *)pwm1_mem, PWM_SIZE);
326 pwm1_mem = NULL;
327 }
328
329 // close /dev/mem
330 if (mem_fd >= 0) {
331 close(mem_fd);
332 mem_fd = -1;
333 }
334}
CONF_SPI0_SCLK_OFFSET
#define CONF_SPI0_SCLK_OFFSET
Definition: check_config.c:67
EPWM_TBCTL_OFFSET
#define EPWM_TBCTL_OFFSET
Time-Base Control Register.
Definition: check_config.c:126
EPWM_AQCTLB_OFFSET
#define EPWM_AQCTLB_OFFSET
Action-Qualifier Control Register for Output B (EPWMxB)
Definition: check_config.c:144
PRU_ICSS_CLKCTRL_OFFSET
#define PRU_ICSS_CLKCTRL_OFFSET
Definition: check_config.c:54
EPWMSS2_CLKCTRL_OFFSET
#define EPWMSS2_CLKCTRL_OFFSET
Definition: check_config.c:53
EPWM_TBCNT_OFFSET
#define EPWM_TBCNT_OFFSET
Time-Base Counter Register.
Definition: check_config.c:132
CONTROL_BASE
#define CONTROL_BASE
CONTROL register base address.
Definition: check_config.c:59
CONTROL_SIZE
#define CONTROL_SIZE
Definition: check_config.c:60
EPWMSS0_CLKCTRL_OFFSET
#define EPWMSS0_CLKCTRL_OFFSET
Definition: check_config.c:52
PWMSS_OFFSET
#define PWMSS_OFFSET
PWMSS module register offset.
Definition: check_config.c:78
CONF_GMPC_AD14_OFFSET
#define CONF_GMPC_AD14_OFFSET
Definition: check_config.c:63
L4LS_CLKSTCTRL_OFFSET
#define L4LS_CLKSTCTRL_OFFSET
Definition: check_config.c:49
PWM1_BASE
#define PWM1_BASE
PWM1 register base address.
Definition: check_config.c:73
CONF_GMPC_A2_OFFSET
#define CONF_GMPC_A2_OFFSET
Definition: check_config.c:65
PWM_SIZE
#define PWM_SIZE
PWM module register map size.
Definition: check_config.c:87
EPWMSS1_CLKCTRL_OFFSET
#define EPWMSS1_CLKCTRL_OFFSET
Definition: check_config.c:51
EPWM_AQCTLA_OFFSET
#define EPWM_AQCTLA_OFFSET
Action-Qualifier Control Register for Output A (EPWMxA)
Definition: check_config.c:142
EPWM_CMPA_OFFSET
#define EPWM_CMPA_OFFSET
Counter-Compare A Register.
Definition: check_config.c:138
CM_PER_BASE
#define CM_PER_BASE
CM_PER register base address.
Definition: check_config.c:46
PWMSS_SYSCONFIG_OFFSET
#define PWMSS_SYSCONFIG_OFFSET
System Configuration Register.
Definition: check_config.c:118
EPWM_TBPRD_OFFSET
#define EPWM_TBPRD_OFFSET
Time-Base Period Register.
Definition: check_config.c:134
CM_PER_SIZE
#define CM_PER_SIZE
Definition: check_config.c:47
PWMSS_CTRL_OFFSET
#define PWMSS_CTRL_OFFSET
Definition: check_config.c:62
CONF_GMPC_A3_OFFSET
#define CONF_GMPC_A3_OFFSET
Definition: check_config.c:66
EPWM_CMPB_OFFSET
#define EPWM_CMPB_OFFSET
Counter-Compare B Register.
Definition: check_config.c:140
main
int main()
Program main fuction.
Definition: check_config.c:147
PWMSS_CLKCONFIG_OFFSET
#define PWMSS_CLKCONFIG_OFFSET
Clock Configuration Register.
Definition: check_config.c:120
L4LS_CLKCTRL_OFFSET
#define L4LS_CLKCTRL_OFFSET
Definition: check_config.c:50
CONF_GMPC_AD15_OFFSET
#define CONF_GMPC_AD15_OFFSET
Definition: check_config.c:64
PWMSS_CLKSTATUS_OFFSET
#define PWMSS_CLKSTATUS_OFFSET
Clock Status Register.
Definition: check_config.c:122
EPWM_OFFSET
#define EPWM_OFFSET
ePWM module register offset
Definition: check_config.c:84
PWM0_BASE
#define PWM0_BASE
PWM0 register base address.
Definition: check_config.c:71