RocketLogger  2.0.1
check_config.c
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1 
32 #include <stddef.h>
33 #include <stdint.h>
34 #include <stdio.h>
35 #include <stdlib.h>
36 
37 #include <fcntl.h>
38 #include <sys/mman.h>
39 #include <sys/stat.h>
40 #include <sys/types.h>
41 #include <unistd.h>
42 
43 
44 // Clock Management module register base addresses, offsets and sizes
46 #define CM_PER_BASE 0x44E00000
47 #define CM_PER_SIZE 0x0400
48 
49 #define L4LS_CLKSTCTRL_OFFSET 0x00
50 #define L4LS_CLKCTRL_OFFSET 0x60
51 #define EPWMSS1_CLKCTRL_OFFSET 0xCC
52 #define EPWMSS0_CLKCTRL_OFFSET 0xD4
53 #define EPWMSS2_CLKCTRL_OFFSET 0xD8
54 #define PRU_ICSS_CLKCTRL_OFFSET 0xE8
55 
56 
57 // CONTROL module register base addresses, offsets and sizes
59 #define CONTROL_BASE 0x44E10000
60 #define CONTROL_SIZE 0x20000
61 
62 #define PWMSS_CTRL_OFFSET 0x664
63 
64 // PWM module register base addresses, offsets and sizes
66 #define PWM0_BASE 0x48300000
68 #define PWM1_BASE 0x48302000
70 #define PWM2_BASE 0x48304000
71 
73 #define PWMSS_OFFSET 0x0000
75 #define ECAP_OFFSET 0x0100
77 #define EQEP_OFFSET 0x0180
79 #define EPWM_OFFSET 0x0200
80 
82 #define PWM_SIZE 0x0260
84 #define PWMSS_SIZE 0x0100
86 #define ECAP_SIZE 0x0080
88 #define EQEP_SIZE 0x0080
90 #define EPWM_SIZE 0x0060
91 
92 // PWMSS sub-module register base addresses, offsets and sizes
93 
95 #define PWMSS0_BASE (PWM0_BASE + PWMSS_OFFSET)
97 #define PWMSS1_BASE (PWM1_BASE + PWMSS_OFFSET)
99 #define PWMSS2_BASE (PWM2_BASE + PWMSS_OFFSET)
100 
101 // ePWM sub-module register base addresses, offsets and sizes
103 #define EPWM0_BASE (PWM0_BASE + EPWM_OFFSET)
105 #define EPWM1_BASE (PWM1_BASE + EPWM_OFFSET)
107 #define EPWM2_BASE (PWM2_BASE + EPWM_OFFSET)
108 
109 // PWMSS configuration register offsets
111 #define PWMSS_IDVER_OFFSET 0x00
113 #define PWMSS_SYSCONFIG_OFFSET 0x04
115 #define PWMSS_CLKCONFIG_OFFSET 0x08
117 #define PWMSS_CLKSTATUS_OFFSET 0x0C
118 
119 // ePWM configuration register offsets
121 #define EPWM_TBCTL_OFFSET 0x00
123 #define EPWM_TBSTS_OFFSET 0x02
125 #define EPWM_TBPHS_OFFSET 0x06
127 #define EPWM_TBCNT_OFFSET 0x08
129 #define EPWM_TBPRD_OFFSET 0x0A
131 #define EPWM_CMPCTL_OFFSET 0x0E
133 #define EPWM_CMPA_OFFSET 0x12
135 #define EPWM_CMPB_OFFSET 0x14
137 #define EPWM_AQCTLA_OFFSET 0x16
139 #define EPWM_AQCTLB_OFFSET 0x18
140 
142 int main() {
144  int mem_fd = -1;
146  volatile uint8_t const *cm_per_mem = NULL;
148  volatile uint8_t const *control_mem = NULL;
150  volatile uint8_t const *pwm0_mem = NULL;
152  volatile uint8_t const *pwm1_mem = NULL;
153 
154  // open /dev/mem for memory mapping
155  mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
156  if (mem_fd < 0) {
157  return EXIT_FAILURE;
158  }
159 
160  // map CM_PER registers
161  cm_per_mem = (volatile uint8_t const *)mmap(0, CM_PER_SIZE, PROT_READ | PROT_WRITE,
162  MAP_SHARED, mem_fd, CM_PER_BASE);
163  if ((void *)cm_per_mem == MAP_FAILED) {
164  return EXIT_FAILURE;
165  }
166 
167  // map CONTROL registers
168  control_mem = (volatile uint8_t const *)mmap(0, CONTROL_SIZE, PROT_READ | PROT_WRITE,
169  MAP_SHARED, mem_fd, CONTROL_BASE);
170  if ((void *)cm_per_mem == MAP_FAILED) {
171  return EXIT_FAILURE;
172  }
173 
174  // map PWM0 registers
175  pwm0_mem = (volatile uint8_t const *)mmap(0, PWM_SIZE, PROT_READ | PROT_WRITE,
176  MAP_SHARED, mem_fd, PWM0_BASE);
177  if ((void *)pwm0_mem == MAP_FAILED) {
178  return EXIT_FAILURE;
179  }
180 
181  // map PWM1 registers
182  pwm1_mem = (volatile uint8_t const *)mmap(0, PWM_SIZE, PROT_READ | PROT_WRITE,
183  MAP_SHARED, mem_fd, PWM1_BASE);
184  if ((void *)pwm1_mem == MAP_FAILED) {
185  return EXIT_FAILURE;
186  }
187 
188  // read memory mapped registers
189 
190  // get pointers of CM_PER registers
191  volatile uint32_t const *cm_per_l4ls_clkstctrl =
192  (volatile uint32_t const *)(cm_per_mem + L4LS_CLKSTCTRL_OFFSET);
193  volatile uint32_t const *cm_per_l4ls_clkctrl =
194  (volatile uint32_t const *)(cm_per_mem + L4LS_CLKCTRL_OFFSET);
195  volatile uint32_t const *cm_per_epwmss0_clkctrl =
196  (volatile uint32_t const *)(cm_per_mem + EPWMSS0_CLKCTRL_OFFSET);
197  volatile uint32_t const *cm_per_epwmss1_clkctrl =
198  (volatile uint32_t const *)(cm_per_mem + EPWMSS1_CLKCTRL_OFFSET);
199  volatile uint32_t const *cm_per_epwmss2_clkctrl =
200  (volatile uint32_t const *)(cm_per_mem + EPWMSS2_CLKCTRL_OFFSET);
201  volatile uint32_t const *cm_per_pru_icss_clkctrl =
202  (volatile uint32_t const *)(cm_per_mem + PRU_ICSS_CLKCTRL_OFFSET);
203 
204  printf("CM_PER registers:\n");
205  printf(" L4LS_CLKSTCTRL: \t0x%08x\n", *cm_per_l4ls_clkstctrl);
206  printf(" L4LS_CLKCTRL: \t0x%08x\n", *cm_per_l4ls_clkctrl);
207  printf(" EPWMSS0_CLKCTRL: \t0x%08x\n", *cm_per_epwmss0_clkctrl);
208  printf(" EPWMSS1_CLKCTRL: \t0x%08x\n", *cm_per_epwmss1_clkctrl);
209  printf(" EPWMSS2_CLKCTRL: \t0x%08x\n", *cm_per_epwmss2_clkctrl);
210  printf(" PRU_ICSS_CLKCTRL:\t0x%08x\n", *cm_per_pru_icss_clkctrl);
211 
212  // get pointers of CONTROL registers
213  volatile uint32_t const *control_pwmss_ctrl =
214  (volatile uint32_t const *)(control_mem + PWMSS_CTRL_OFFSET);
215 
216  printf("CONTROL registers:\n");
217  printf(" PWMSS_CTRL: \t0x%08x\n", *control_pwmss_ctrl);
218 
219  // get pointers of PWMSS0 registers
220  volatile uint32_t const *pwmss0_sysconfig =
221  (volatile uint32_t const *)(pwm0_mem + PWMSS_OFFSET + PWMSS_SYSCONFIG_OFFSET);
222  volatile uint32_t const *pwmss0_clkconfig =
223  (volatile uint32_t const *)(pwm0_mem + PWMSS_OFFSET + PWMSS_CLKCONFIG_OFFSET);
224  volatile uint32_t const *pwmss0_clkstatus =
225  (volatile uint32_t const *)(pwm0_mem + PWMSS_OFFSET + PWMSS_CLKSTATUS_OFFSET);
226 
227  volatile uint16_t const *epwm0_tbctl =
228  (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_TBCTL_OFFSET);
229  volatile uint16_t const *epwm0_tbcnt =
230  (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_TBCNT_OFFSET);
231  volatile uint16_t const *epwm0_tbprd =
232  (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_TBPRD_OFFSET);
233  volatile uint16_t const *epwm0_cmpa =
234  (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_CMPA_OFFSET);
235  volatile uint16_t const *epwm0_cmpb =
236  (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_CMPB_OFFSET);
237  volatile uint16_t const *epwm0_aqctla =
238  (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_AQCTLA_OFFSET);
239  volatile uint16_t const *epwm0_aqctlb =
240  (volatile uint16_t const *)(pwm0_mem + EPWM_OFFSET + EPWM_AQCTLB_OFFSET);
241 
242  printf("PWMSS0 registers:\n");
243  printf(" SYSCONFIG: \t0x%08x\n", *pwmss0_sysconfig);
244  printf(" CLKCONFIG: \t0x%08x\n", *pwmss0_clkconfig);
245  printf(" CLKSTATUS: \t0x%08x\n", *pwmss0_clkstatus);
246  printf(" ePWM0 registers:\n");
247  printf(" TBCTL: \t0x%04x\n", *epwm0_tbctl);
248  printf(" TBCNT: \t0x%04x\n", *epwm0_tbcnt);
249  printf(" TBPRD: \t0x%04x\n", *epwm0_tbprd);
250  printf(" CMPA: \t0x%04x\n", *epwm0_cmpa);
251  printf(" CMPB: \t0x%04x\n", *epwm0_cmpb);
252  printf(" AQCTLA:\t0x%04x\n", *epwm0_aqctla);
253  printf(" AQCTLB:\t0x%04x\n", *epwm0_aqctlb);
254 
255  // get pointers of PWMSS1 registers
256  volatile uint32_t const *pwmss1_sysconfig =
257  (volatile uint32_t const *)(pwm1_mem + PWMSS_OFFSET + PWMSS_SYSCONFIG_OFFSET);
258  volatile uint32_t const *pwmss1_clkconfig =
259  (volatile uint32_t const *)(pwm1_mem + PWMSS_OFFSET + PWMSS_CLKCONFIG_OFFSET);
260  volatile uint32_t const *pwmss1_clkstatus =
261  (volatile uint32_t const *)(pwm1_mem + PWMSS_OFFSET + PWMSS_CLKSTATUS_OFFSET);
262 
263  volatile uint16_t const *epwm1_tbctl =
264  (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_TBCTL_OFFSET);
265  volatile uint16_t const *epwm1_tbcnt =
266  (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_TBCNT_OFFSET);
267  volatile uint16_t const *epwm1_tbprd =
268  (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_TBPRD_OFFSET);
269  volatile uint16_t const *epwm1_cmpa =
270  (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_CMPA_OFFSET);
271  volatile uint16_t const *epwm1_cmpb =
272  (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_CMPB_OFFSET);
273  volatile uint16_t const *epwm1_aqctla =
274  (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_AQCTLA_OFFSET);
275  volatile uint16_t const *epwm1_aqctlb =
276  (volatile uint16_t const *)(pwm1_mem + EPWM_OFFSET + EPWM_AQCTLB_OFFSET);
277 
278  printf("PWMSS1 registers:\n");
279  printf(" SYSCONFIG: \t0x%08x\n", *pwmss1_sysconfig);
280  printf(" CLKCONFIG: \t0x%08x\n", *pwmss1_clkconfig);
281  printf(" CLKSTATUS: \t0x%08x\n", *pwmss1_clkstatus);
282  printf(" ePWM1 registers:\n");
283  printf(" TBCTL: \t0x%04x\n", *epwm1_tbctl);
284  printf(" TBCNT: \t0x%04x\n", *epwm1_tbcnt);
285  printf(" TBPRD: \t0x%04x\n", *epwm1_tbprd);
286  printf(" CMPA: \t0x%04x\n", *epwm1_cmpa);
287  printf(" CMPB: \t0x%04x\n", *epwm1_cmpb);
288  printf(" AQCTLA:\t0x%04x\n", *epwm1_aqctla);
289  printf(" AQCTLB:\t0x%04x\n", *epwm1_aqctlb);
290 
291  // unmap memory
292  if (cm_per_mem != NULL) {
293  munmap((void *)cm_per_mem, CM_PER_SIZE);
294  cm_per_mem = NULL;
295  }
296  if (control_mem != NULL) {
297  munmap((void *)control_mem, CONTROL_SIZE);
298  control_mem = NULL;
299  }
300  if (pwm0_mem != NULL) {
301  munmap((void *)pwm0_mem, PWM_SIZE);
302  pwm0_mem = NULL;
303  }
304  if (pwm1_mem != NULL) {
305  munmap((void *)pwm1_mem, PWM_SIZE);
306  pwm1_mem = NULL;
307  }
308 
309  // close /dev/mem
310  if (mem_fd >= 0) {
311  close(mem_fd);
312  mem_fd = -1;
313  }
314 }
EPWM_TBCTL_OFFSET
#define EPWM_TBCTL_OFFSET
Time-Base Control Register.
Definition: check_config.c:121
EPWM_AQCTLB_OFFSET
#define EPWM_AQCTLB_OFFSET
Action-Qualifier Control Register for Output B (EPWMxB)
Definition: check_config.c:139
PRU_ICSS_CLKCTRL_OFFSET
#define PRU_ICSS_CLKCTRL_OFFSET
Definition: check_config.c:54
EPWMSS2_CLKCTRL_OFFSET
#define EPWMSS2_CLKCTRL_OFFSET
Definition: check_config.c:53
EPWM_TBCNT_OFFSET
#define EPWM_TBCNT_OFFSET
Time-Base Counter Register.
Definition: check_config.c:127
CONTROL_BASE
#define CONTROL_BASE
CONTROL register base address.
Definition: check_config.c:59
CONTROL_SIZE
#define CONTROL_SIZE
Definition: check_config.c:60
EPWMSS0_CLKCTRL_OFFSET
#define EPWMSS0_CLKCTRL_OFFSET
Definition: check_config.c:52
PWMSS_OFFSET
#define PWMSS_OFFSET
PWMSS module register offset.
Definition: check_config.c:73
L4LS_CLKSTCTRL_OFFSET
#define L4LS_CLKSTCTRL_OFFSET
Definition: check_config.c:49
PWM1_BASE
#define PWM1_BASE
PWM1 register base address.
Definition: check_config.c:68
PWM_SIZE
#define PWM_SIZE
PWM module register map size.
Definition: check_config.c:82
EPWMSS1_CLKCTRL_OFFSET
#define EPWMSS1_CLKCTRL_OFFSET
Definition: check_config.c:51
EPWM_AQCTLA_OFFSET
#define EPWM_AQCTLA_OFFSET
Action-Qualifier Control Register for Output A (EPWMxA)
Definition: check_config.c:137
EPWM_CMPA_OFFSET
#define EPWM_CMPA_OFFSET
Counter-Compare A Register.
Definition: check_config.c:133
CM_PER_BASE
#define CM_PER_BASE
CM_PER register base address.
Definition: check_config.c:46
PWMSS_SYSCONFIG_OFFSET
#define PWMSS_SYSCONFIG_OFFSET
System Configuration Register.
Definition: check_config.c:113
EPWM_TBPRD_OFFSET
#define EPWM_TBPRD_OFFSET
Time-Base Period Register.
Definition: check_config.c:129
CM_PER_SIZE
#define CM_PER_SIZE
Definition: check_config.c:47
PWMSS_CTRL_OFFSET
#define PWMSS_CTRL_OFFSET
Definition: check_config.c:62
EPWM_CMPB_OFFSET
#define EPWM_CMPB_OFFSET
Counter-Compare B Register.
Definition: check_config.c:135
main
int main()
Program main fuction.
Definition: check_config.c:142
PWMSS_CLKCONFIG_OFFSET
#define PWMSS_CLKCONFIG_OFFSET
Clock Configuration Register.
Definition: check_config.c:115
L4LS_CLKCTRL_OFFSET
#define L4LS_CLKCTRL_OFFSET
Definition: check_config.c:50
PWMSS_CLKSTATUS_OFFSET
#define PWMSS_CLKSTATUS_OFFSET
Clock Status Register.
Definition: check_config.c:117
EPWM_OFFSET
#define EPWM_OFFSET
ePWM module register offset
Definition: check_config.c:79
PWM0_BASE
#define PWM0_BASE
PWM0 register base address.
Definition: check_config.c:66